Villach, Austria

Your Role

• Define and execute comprehensive verification strategies for Mixed-Signal designs
• Design and refine scalable verification environments using SystemVerilog, UVM, and Constrained Random methodologies
• Run rigorous tests at RTL and gate levels, identifying and resolving issues
• Lead verification engineering efforts and coordinate cross-functional initiatives
• Partner with analog/digital designers and verification peers
• Guide junior engineers, consultants, and students

Your Profile

• University degree in Electrical Engineering, Computer Science, or related field
• Over 6 years in Digital Verification with leadership experience
• Expert knowledge of SystemVerilog, UVM, and verification tools (Xcelium, Verdi, vManager)
• Proficient in Python and GIT
• Strong English; German preferred

Bewerben Sie sich über den "Jetzt bewerben"-Button.